Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain.
A Flash device that utilizes the ONO structure is a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) cell. Referring to FIG. 1, a known MONOS cell, generally referred to as 10, includes at least one bit-line oxide 12, a word line 14 and an ONO structure 16 which function together to determine the location of a charge stored in memory. The bit-line oxide 12 and the ONO structure 16 overlie a silicon wafer 17.
A problem exists with known MONOS cell fabrication techniques in that as the MONOS cells decrease in size, formation of the bit-line oxide 12 causes a bird's beak 18 of the ONO structure 16 to form and increasingly encroach the word line 14. The bird's beak 18 is an undesired result of the fabrication process for several reasons. For example, the bird's beak 18 causes an increase in surface area which enlarges the circuit. In addition, at a performance level, the bird's beak 18 can induce fatal stress damage to the silicon wafer 17, especially during bit-line oxidation steps. The stress results, for example, from a mismatch in thermal expansion properties between the ONO structure 18 and the silicon wafer 17.
Therefore, while recent advances in MONOS cell technology have enabled memory designers to reduce the size of the MONOS cells, numerous challenges exist in the fabrication of material layers within these devices. In particular, a fabrication process of MONOS cells should accommodate a reduction in size of the MONOS cell while avoiding a bird's beak formation. Accordingly, advances in MONOS cell fabrication technology are necessary to eliminate the bird's beak and insure high quality MONOS cell devices.